PackagesFind USE flags
USE Flag Search Results for cpu_flags_x86
Use VIA padlock instructions, detected at run time, code still works on non-padlock processorsEnable the XOP instruction setUse the MMX instruction setAdds support for F16C instruction set for converting between half-precision and single-precision floatsUse the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)Adds support for Advanced Vector Extensions instructionsUse the SHA-NI instruction setUse the SSE instruction setUse the Fused Multiply Add 4 instruction setEnable support for Intel's AES instruction set (AES-NI)Use the SSE2 instruction setUse the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)Enable the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)Enable the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)Adds support for Advanced Vector Extensions 2 instructionsEnable SSE4a instruction supportUse the 3DNow! instruction setUse the SSSE3 instruction set (NOT sse3/pni)Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)Enable SSE4.2 instruction supportEnable SSE4.1 instruction supportUse the RDRAND instruction for generating random numbersEnable popcnt instruction support ([abm] or [popcnt] in cpuinfo)Use VIA padlock instructions ([phe] in cpuinfo)Adds support for AVX-512 Foundation instructionsUse AVX-512 conflict detection instructionsUse Advanced Matrix Extensions tile computational operations on 8-bit integersUse AVX-512 double- and quad-word instructionsUse the Enhanced 3DNow! instruction setUse AVX-512 vector-length instructionsUse Advanced Matrix Extensions tile architecture supportUse AVX-512 byte- and word instructionsUse AVX-512 exponential and reciprocal instructionsUse Advanced Matrix Extensions tile computational operations on bfloat16 numbersUse AVX (VEX-encoded) versions of the Vector Neural Network InstructionsUse AVX-512 prefetch instructionsUse AVX-512 vector byte manipulation instructionsUse general-purpose numeric operations for 16-bit half-precision instruction setUse AVX-512 Integer Fused Multiply-Add instruction setUse Vector Carry-Less Multiplication of Quadwords instruction setUse AVX-512 BFloat16 instruction setUse vector neural network instructions for 8- and 16-bit multiply-add operationsUse AVX-512 Vector Bit Manipulation Instructions 2Use AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction setUse AVX-512 Vector Neural Network Instructions Word Variable PrecisionUse AVX-512 Bit Algorithms instruction setUse AVX-512 Vector Population Count Doubleword and Quadword instruction setUse AVX-512 Intersect instruction set