Use the CRC32 instruction set

Other “cpu_flags_arm” USE_EXPAND flag values

Use FlagDescription
cpu_flags_arm_aesUse the AES cryptography instruction set
cpu_flags_arm_asimddpUse the Advanced SIMD dot product instructions
cpu_flags_arm_crc32Use the CRC32 instruction set
cpu_flags_arm_edspUse the enhanced DSP instructions (ARMv*E and ARMv6+)
cpu_flags_arm_i8mmUse the AArch64 Int8 matrix multiplication instructions
cpu_flags_arm_iwmmxtUse the iwMMXt instruction set
cpu_flags_arm_iwmmxt2Use the iwMMXt2 instruction set
cpu_flags_arm_neonUse the NEON (ASIMD) instruction set
cpu_flags_arm_sha1Use the SHA-1 cryptography instruction set
cpu_flags_arm_sha2Use the SHA-2 cryptography instruction set
cpu_flags_arm_sm4Use the SM4 cryptography instruction set
cpu_flags_arm_sveUse the Scalable Vector Extension instruction set
cpu_flags_arm_thumbEnable Thumb instruction set (ARMv*T and ARMv6+)
cpu_flags_arm_thumb2Enable Thumb-2 instruction set (ARMv*T2 and ARMv7+)
cpu_flags_arm_v4Use instructions added in ARMv4
cpu_flags_arm_v5Use instructions added in ARMv5
cpu_flags_arm_v6Use instructions added in ARMv6
cpu_flags_arm_v7Use instructions added in ARMv7
cpu_flags_arm_v8Use instructions added in ARMv8
cpu_flags_arm_vfpUse the VFP version 2 instruction set
cpu_flags_arm_vfp-d32Indicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)
cpu_flags_arm_vfpv3Use the VFP version 3 instruction set
cpu_flags_arm_vfpv4Use the VFP version 4 instruction set

All packages providing a “cpu_flags_arm_crc32” USE flag (4)