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for cpu_flags_arm
cpu_flags_arm_v8
Use instructions added in ARMv8
cpu_flags_arm_v6
Use instructions added in ARMv6
cpu_flags_arm_aes
Use the AES cryptography instruction set
cpu_flags_arm_v5
Use instructions added in ARMv5
cpu_flags_arm_v4
Use instructions added in ARMv4
cpu_flags_arm_v7
Use instructions added in ARMv7
cpu_flags_arm_sve
Use the Scalable Vector Extension instruction set
cpu_flags_arm_sm4
Use the SM4 cryptography instruction set
cpu_flags_arm_vfp
Use the VFP version 2 instruction set
cpu_flags_arm_sve2
Use the Scalable Vector Extension 2 instruction set
cpu_flags_arm_crc32
Use the CRC32 instruction set
cpu_flags_arm_neon
Use the NEON instruction set
cpu_flags_arm_edsp
Use the enhanced DSP instructions (ARMv*E and ARMv6+)
cpu_flags_arm_sha2
Use the SHA-2 cryptography instruction set
cpu_flags_arm_sha1
Use the SHA-1 cryptography instruction set
cpu_flags_arm_asimd
Use the Advanced SIMD instructions (NEON with ARMv8 extensions)
cpu_flags_arm_i8mm
Use the AArch64 Int8 matrix multiplication instructions
cpu_flags_arm_vfpv4
Use the VFP version 4 instruction set
cpu_flags_arm_thumb
Enable Thumb instruction set (ARMv*T and ARMv6+)
cpu_flags_arm_vfpv3
Use the VFP version 3 instruction set
cpu_flags_arm_asimdhp
Use the Advanced SIMD half-precision & vector arithmetics
cpu_flags_arm_iwmmxt
Use the iwMMXt instruction set
cpu_flags_arm_asimddp
Use the Advanced SIMD dot product instructions
cpu_flags_arm_thumb2
Enable Thumb-2 instruction set (ARMv*T2 and ARMv7+)
cpu_flags_arm_asimdfhm
Use the Advanced SIMD single- & half-precision multiply
cpu_flags_arm_iwmmxt2
Use the iwMMXt2 instruction set
cpu_flags_arm_vfp-d32
Indicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)
cpu_flags_arm_neon-fp16
Use the NEON intruction set with half word loads / store support
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