PackagesFind USE flags
USE Flag Search Results for cpu_flags_
Use VIA padlock instructions, detected at run time, code still works on non-padlock processorsUse the AES cryptography instruction setUse instructions added in ARMv8Enable the XOP instruction setUse instructions added in ARMv6Use instructions added in ARMv5Use instructions added in ARMv7Use instructions added in ARMv4Use the MMX instruction setUse the SM4 cryptography instruction setUse the Vector Scalar Extension instruction set (POWER7 and later)Use the SHA-NI instruction setAdds support for F16C instruction set for converting between half-precision and single-precision floatsUse the Scalable Vector Extension instruction setUse the VFP version 2 instruction setUse the SSE instruction setUse the Fused Multiply Add 4 instruction setEnable support for Intel's AES instruction set (AES-NI)Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)Adds support for Advanced Vector Extensions instructionsAdds support for Advanced Vector Extensions 2 instructionsUse the enhanced DSP instructions (ARMv*E and ARMv6+)Use the SHA-2 cryptography instruction setUse the Vector Scalar Extension v.2 instruction set (POWER8 and later)Use the Vector Scalar Extension v.3 instruction set (POWER9 and later)Use the Advanced SIMD instructions (NEON with ARMv8 extensions)Enable the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)Use the AArch64 Int8 matrix multiplication instructionsUse the Scalable Vector Extension 2 instruction setUse the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)Use the SSE2 instruction setUse the CRC32 instruction setUse the Vector Scalar Extension v.4 instruction set (POWER10 and later)Use the SHA-1 cryptography instruction setUse the NEON instruction setEnable the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)Use the SSSE3 instruction set (NOT sse3/pni)Use the 3DNow! instruction setUse the VFP version 3 instruction setEnable SSE4a instruction supportUse the VFP version 4 instruction setEnable Thumb instruction set (ARMv*T and ARMv6+)Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)Use the RDRAND instruction for generating random numbersEnable SSE4.2 instruction supportEnable Thumb-2 instruction set (ARMv*T2 and ARMv7+)Use the Advanced SIMD half-precision & vector arithmeticsUse the iwMMXt instruction setUse the Advanced SIMD dot product instructionsEnable popcnt instruction support ([abm] or [popcnt] in cpuinfo)Enable SSE4.1 instruction supportUse the Advanced SIMD single- & half-precision multiplyIndicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)Use VIA padlock instructions ([phe] in cpuinfo)Use the iwMMXt2 instruction setUse the AltiVec/VMX instruction setAdds support for AVX-512 Foundation instructionsUse AVX-512 exponential and reciprocal instructionsUse AVX-512 double- and quad-word instructionsUse AVX-512 prefetch instructionsUse AVX-512 byte- and word instructionsUse AVX-512 conflict detection instructionsUse Advanced Matrix Extensions tile computational operations on bfloat16 numbersUse AVX (VEX-encoded) versions of the Vector Neural Network InstructionsUse the NEON intruction set with half word loads / store supportUse AVX-512 vector-length instructionsUse Advanced Matrix Extensions tile architecture supportUse the Enhanced 3DNow! instruction setUse Advanced Matrix Extensions tile computational operations on 8-bit integersUse general-purpose numeric operations for 16-bit half-precision instruction setUse AVX-512 vector byte manipulation instructionsUse AVX-512 Integer Fused Multiply-Add instruction setUse Vector Carry-Less Multiplication of Quadwords instruction setUse AVX-512 BFloat16 instruction setUse vector neural network instructions for 8- and 16-bit multiply-add operationsUse AVX-512 Vector Bit Manipulation Instructions 2Use AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction setUse AVX-512 Vector Neural Network Instructions Word Variable PrecisionUse AVX-512 Bit Algorithms instruction setUse AVX-512 Vector Population Count Doubleword and Quadword instruction setUse AVX-512 Intersect instruction set