PackagesFind USE flags
USE Flag Search Results for cpu_flags_
Use VIA padlock instructions, detected at run time, code still works on non-padlock processorsUse instructions added in ARMv7Use instructions added in ARMv4Use instructions added in ARMv6Use instructions added in ARMv5Use the AES cryptography instruction setUse instructions added in ARMv8Enable the XOP instruction setUse the SM4 cryptography instruction setUse the Scalable Vector Extension instruction setUse the SHA-NI instruction setUse the VFP version 2 instruction setUse the Fused Multiply Add 4 instruction setUse the MMX instruction setAdds support for F16C instruction set for converting between half-precision and single-precision floatsEnable support for Intel's AES instruction set (AES-NI)Use the Vector Scalar Extension instruction set (POWER7 and later)Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)Adds support for Advanced Vector Extensions instructionsUse the SSE instruction setEnable the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)Use the SSE2 instruction setUse the NEON instruction setUse the Vector Scalar Extension v.2 instruction set (POWER8 and later)Use the Vector Scalar Extension v.3 instruction set (POWER9 and later)Adds support for Advanced Vector Extensions 2 instructionsUse the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)Use the AArch64 Int8 matrix multiplication instructionsUse the Vector Scalar Extension v.4 instruction set (POWER10 and later)Use the Advanced SIMD instructions (NEON with ARMv8 extensions)Use the CRC32 instruction setUse the Scalable Vector Extension 2 instruction setUse the SHA-1 cryptography instruction setUse the enhanced DSP instructions (ARMv*E and ARMv6+)Enable the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)Use the SHA-2 cryptography instruction setUse the SSSE3 instruction set (NOT sse3/pni)Use the VFP version 4 instruction setUse the VFP version 3 instruction setEnable Thumb instruction set (ARMv*T and ARMv6+)Enable SSE4a instruction supportUse the 3DNow! instruction setUse the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)Use the Advanced SIMD half-precision & vector arithmeticsEnable SSE4.2 instruction supportEnable SSE4.1 instruction supportUse the RDRAND instruction for generating random numbersUse Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)Enable Thumb-2 instruction set (ARMv*T2 and ARMv7+)Enable popcnt instruction support ([abm] or [popcnt] in cpuinfo)Use the iwMMXt instruction setUse the Advanced SIMD dot product instructionsAdds support for AVX-512 Foundation instructionsUse the iwMMXt2 instruction setUse the Advanced SIMD single- & half-precision multiplyUse VIA padlock instructions ([phe] in cpuinfo)Indicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)Use the AltiVec/VMX instruction setUse the Enhanced 3DNow! instruction setUse AVX-512 prefetch instructionsUse Advanced Matrix Extensions tile architecture supportUse AVX-512 double- and quad-word instructionsUse Advanced Matrix Extensions tile computational operations on 8-bit integersUse AVX-512 byte- and word instructionsUse AVX-512 exponential and reciprocal instructionsUse the NEON intruction set with half word loads / store supportUse AVX (VEX-encoded) versions of the Vector Neural Network InstructionsUse AVX-512 vector-length instructionsUse AVX-512 conflict detection instructionsUse Advanced Matrix Extensions tile computational operations on bfloat16 numbersUse general-purpose numeric operations for 16-bit half-precision instruction setUse AVX-512 vector byte manipulation instructionsUse Vector Carry-Less Multiplication of Quadwords instruction setUse AVX-512 Integer Fused Multiply-Add instruction setUse AVX-512 BFloat16 instruction setUse vector neural network instructions for 8- and 16-bit multiply-add operationsUse AVX-512 Vector Bit Manipulation Instructions 2Use AVX-512 Bit Algorithms instruction setUse AVX-512 Vector Neural Network Instructions Word Variable PrecisionUse AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction setUse AVX-512 Vector Population Count Doubleword and Quadword instruction setUse AVX-512 Intersect instruction set