PackagesFind USE flags
USE Flag Search Results for cpu_flags_
Use VIA padlock instructions, detected at run time, code still works on non-padlock processorsUse instructions added in ARMv8Use instructions added in ARMv6Use instructions added in ARMv7Use the AES cryptography instruction setEnable the XOP instruction setUse instructions added in ARMv5Use instructions added in ARMv4Use the SSE instruction setAdds support for Advanced Vector Extensions instructionsUse the MMX instruction setUse the SHA-NI instruction setUse the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)Use the SM4 cryptography instruction setUse the VFP version 2 instruction setUse the Scalable Vector Extension instruction setUse the Fused Multiply Add 4 instruction setAdds support for F16C instruction set for converting between half-precision and single-precision floatsUse the Vector Scalar Extension instruction set (POWER7 and later)Enable support for Intel's AES instruction set (AES-NI)Use the NEON instruction setUse the Vector Scalar Extension v.2 instruction set (POWER8 and later)Use the Vector Scalar Extension v.3 instruction set (POWER9 and later)Use the Vector Scalar Extension v.4 instruction set (POWER10 and later)Use the SSE2 instruction setUse the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)Enable the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)Use the SHA-2 cryptography instruction setUse the CRC32 instruction setUse the Scalable Vector Extension 2 instruction setUse the Advanced SIMD instructions (NEON with ARMv8 extensions)Use the AArch64 Int8 matrix multiplication instructionsUse the SHA-1 cryptography instruction setUse the enhanced DSP instructions (ARMv*E and ARMv6+)Enable the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)Adds support for Advanced Vector Extensions 2 instructionsUse the 3DNow! instruction setUse the VFP version 4 instruction setUse the SSSE3 instruction set (NOT sse3/pni)Enable Thumb instruction set (ARMv*T and ARMv6+)Use the VFP version 3 instruction setEnable SSE4a instruction supportEnable SSE4.2 instruction supportUse the Advanced SIMD half-precision & vector arithmeticsUse the iwMMXt instruction setEnable Thumb-2 instruction set (ARMv*T2 and ARMv7+)Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)Use the RDRAND instruction for generating random numbersEnable SSE4.1 instruction supportEnable popcnt instruction support ([abm] or [popcnt] in cpuinfo)Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)Use the Advanced SIMD dot product instructionsUse the Advanced SIMD single- & half-precision multiplyUse the iwMMXt2 instruction setUse the AltiVec/VMX instruction setUse VIA padlock instructions ([phe] in cpuinfo)Adds support for AVX-512 Foundation instructionsIndicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)Use AVX-512 vector-length instructionsUse Advanced Matrix Extensions tile computational operations on bfloat16 numbersUse the Enhanced 3DNow! instruction setUse AVX-512 byte- and word instructionsUse AVX-512 exponential and reciprocal instructionsUse AVX-512 prefetch instructionsUse AVX-512 conflict detection instructionsUse AVX (VEX-encoded) versions of the Vector Neural Network InstructionsUse AVX-512 double- and quad-word instructionsUse Advanced Matrix Extensions tile computational operations on 8-bit integersUse Advanced Matrix Extensions tile architecture supportUse the NEON intruction set with half word loads / store supportUse AVX-512 Integer Fused Multiply-Add instruction setUse Vector Carry-Less Multiplication of Quadwords instruction setUse AVX-512 vector byte manipulation instructionsUse general-purpose numeric operations for 16-bit half-precision instruction setUse AVX-512 BFloat16 instruction setUse vector neural network instructions for 8- and 16-bit multiply-add operationsUse AVX-512 Vector Bit Manipulation Instructions 2Use AVX-512 Vector Neural Network Instructions Word Variable PrecisionUse AVX-512 Bit Algorithms instruction setUse AVX-512 Fused Multiply-Accumulate Packed Single Precision instruction setUse AVX-512 Vector Population Count Doubleword and Quadword instruction setUse AVX-512 Intersect instruction set