USE flags

cpu_flags_arm_sha2

Use the SHA-2 cryptography instruction set

cpu_flags_arm_vfp-d32

Indicate that the FPU has 32 64-bit VFP (v3+) registers (16 otherwise)

cpu_flags_arm_iwmmxt2

Use the iwMMXt2 instruction set

cpu_flags_arm_aes

Use the AES cryptography instruction set

cpu_flags_arm_crc32

Use the CRC32 instruction set

cpu_flags_arm_edsp

Use the enhanced DSP instructions (ARMv*E and ARMv6+)

cpu_flags_arm_iwmmxt

Use the iwMMXt instruction set

cpu_flags_arm_neon

Use the NEON (ASIMD) instruction set

cpu_flags_arm_vfpv3

Use the VFP version 3 instruction set

cpu_flags_arm_vfpv4

Use the VFP version 4 instruction set

cpu_flags_arm_v5

Use instructions added in ARMv5

cpu_flags_arm_thumb

Enable Thumb instruction set (ARMv*T and ARMv6+)

cpu_flags_x86_f16c

Adds support for F16C instruction set for converting between half-precision and single-precision floats

cpu_flags_ppc_vsx

Use the Vector Scalar Extension instruction set (POWER7 and later)

cpu_flags_arm_thumb2

Enable Thumb-2 instruction set (ARMv*T2 and ARMv7+)

cpu_flags_arm_v4

Use instructions added in ARMv4

cpu_flags_arm_v8

Use instructions added in ARMv8

cpu_flags_arm_vfp

Use the VFP version 2 instruction set

cpu_flags_x86_3dnow

Use the 3DNow! instruction set

cpu_flags_x86_3dnowext

Use the Enhanced 3DNow! instruction set

cpu_flags_x86_aes

Enable support for Intel's AES instruction set (AES-NI)

cpu_flags_x86_avx

Adds support for Advanced Vector Extensions instructions

cpu_flags_x86_avx2

Adds support for Advanced Vector Extensions 2 instructions

cpu_flags_x86_fma3

Use the Fused Multiply Add 3 instruction set ([fma] in cpuinfo)

cpu_flags_x86_fma4

Use the Fused Multiply Add 4 instruction set

cpu_flags_x86_mmx

Use the MMX instruction set

cpu_flags_x86_mmxext

Use the Extended MMX instruction set (a subset of SSE) ([mmxext] or [sse] in cpuinfo)

cpu_flags_x86_padlock

Use VIA padlock instructions ([phe] in cpuinfo)

cpu_flags_x86_pclmul

Use Carry-less Multiplication instructions ([pclmulqdq] in cpuinfo)

cpu_flags_x86_popcnt

Enable popcnt instruction support ([abm] or [popcnt] in cpuinfo)

cpu_flags_x86_rdrand

Use the RDRAND instruction for generating random numbers

cpu_flags_x86_sha

Use the SHA-NI instruction set

cpu_flags_x86_sse

Use the SSE instruction set

cpu_flags_x86_sse2

Use the SSE2 instruction set

cpu_flags_x86_sse3

Use the SSE3 instruction set ([pni] in cpuinfo, NOT ssse3)

cpu_flags_x86_sse4_1

Enable SSE4.1 instruction support

cpu_flags_x86_sse4_2

Enable SSE4.2 instruction support

cpu_flags_x86_sse4a

Enable SSE4a instruction support

cpu_flags_x86_ssse3

Use the SSSE3 instruction set (NOT sse3/pni)

cpu_flags_x86_xop

Enable the XOP instruction set

cpu_flags_ppc_altivec

Use the AltiVec/VMX instruction set

cpu_flags_ppc_vsx2

Use the Vector Scalar Extension v.2 instruction set (POWER8 and later)

cpu_flags_ppc_vsx3

Use the Vector Scalar Extension v.3 instruction set (POWER9 and later)

cpu_flags_x86_avx512dq

Use AVX-512 double- and quad-word instructions

cpu_flags_x86_avx512f

Adds support for AVX-512 Foundation instructions

cpu_flags_x86_avx512vl

Use AVX-512 vector-length instructions

cpu_flags_arm_sha1

Use the SHA-1 cryptography instruction set

cpu_flags_arm_v6

Use instructions added in ARMv6

cpu_flags_arm_v7

Use instructions added in ARMv7

cpu_flags_x86_padlock

Use VIA padlock instructions, detected at run time, code still works on non-padlock processors